The present invention relates to a clock phase adjustment method, and an integrated circuit and a method for designing the integrated circuit.
When writing data into a synchronous DRAM (Synchronous Dynamic Random Access Memory, hereinafter referred to as a SDRAM) or reading data from the SDRAM (hereinafter referred to as data access), it is difficult to make appropriate timing because of a high-speed operating clock. Therefore, conventionally, a LSI that makes data access to the SDRAM is fabricated initially, and then the phase of the clock is adjusted by trial and error.
Further, Japanese Published Patent Application No. Hei.9-185427 discloses a clock phase adjustment circuit and a clock phase adjustment method for making timing of access to a SDRAM.
FIG. 13 is a circuit diagram illustrating a memory interface circuit to which a clock phase adjustment circuit as disclosed in Japanese Published Patent Application No. Hei.9-185427 is applied. A memory interface device 700 comprises a clock frequency converter 710, two input buffers 711 and 720, a clock phase adjustment circuit 712, three output buffers 715, 717, and 719, and three flip-flops (FF) 716, 718, and 721. The interface device 700 outputs an external clock signal, a SDRAM command, and data to a SDRAM 702.
The clock phase adjustment circuit 712 is a circuit for adjusting the phase of a clock signal to execute appropriate data access to the SDRAM 702, and it inverts the phase of a clock signal as a reference of operation by 180 degrees, and outputs the clock signal to the SDRAM 702. The clock phase adjustment circuit 712 is composed of an inverter 713, a phase converter 714, and a selector 744.
The phase converter 714 is provided with clocks having different delay values. After the memory interface device 700 is connected to the SDRAM 702, operable clocks are tested by appropriate means, and a clock, which is judged as being appropriate on the basis of the result of the text, is selected.
The conventional clock phase adjustment is carried out by trial and error after fabricating an actual LSI. That is, since the design engineer adjusts the clock phase by repeating trial and error after the LSI is fabricated, the process steps relating to the fabrication of the LSI are complicated.
Further, in the interface device 700 as disclosed in Japanese Published Patent Application No. Hei.9-185427, a lot of delay elements relating to clock phase adjustment are required, whereby the circuit scale is increased, and the power consumption is also increased.
Further, since the data inputted to the interface device 700 passes through various circuits and buffers before it is outputted from the device 700, when the interface device 700 is implemented in a practical LSI, the delays of clocks might be greatly different from those expected, resulting in difficulty in determining the delay values of the delay elements. In this case, although determination of the delay values may be facilitated by preparing more delay clocks, this causes a new problem that the circuit scale and the power consumption are further increased.
Furthermore, since the delay values cannot be known unless the interface device 700 is actually connected to the SDRAM 702, it is necessary to perform, after connecting the interface circuit 700 to the SDRAM 702, a test of data transfer to select a clock of optimum delay value, whereby the number of process steps relating to the circuit fabrication increases.
Moreover, since external factors (wiring delay, external load, etc.) are not considered in the interface device 700, the precision is degraded. Further, in order to consider the external factors, a test of data transfer must be performed for every substrate to select a clock, whereby the number of process steps relating to the circuit fabrication increases.
The present invention provides a clock phase adjustment method that realizes clock phase adjustment in the designing stage, with reduced number of process steps relating to fabrication of a device that makes access to an external memory, without performing phase adjustment by trial and error, and without performing a test for clock phase adjustment. This clock phase adjustment method realizes supply of more reliable clocks, with minimum required circuits, even in perfect synchronous design, and realizes automatic clock phase adjustment even when a feedback clock system is employed.
Further, the present invention provides an integrated circuit and a design method thereof, which realize data access on the basis of a high-speed operating clock, without requiring complicated structure like the conventional circuit.
In order to achieve the above-mentioned objects, an integrated circuit according to the present invention has the following construction. That is, an integrated circuit, which makes data access to an external memory in synchronization with a clock, comprises: a clock generator for generating the clock; at least one first clock buffer for driving the clock as an external clock; at least one second clock buffer for driving the clock as an internal clock; a clock output buffer for outputting the external clock to the external memory; a data output flip-flop for outputting data to he outputted to the external memory, in synchronization with the internal clock; and an input flip-flop for capturing data outputted from the external memory, in synchronization with the internal clock; wherein a value of a phase difference D obtained by subtracting xe2x80x9cthe time from when the external clock is outputted from the clock generator to when it reaches the clock output bufferxe2x80x9d from xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the data output flip-flopxe2x80x9d is set so as to satisfy first to fourth conditions as follows: first condition: a first value obtained by subtracting xe2x80x9cthe time from when the external clock is outputted from the clock generator to when it reaches the external memoryxe2x80x9d from the sum of xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the data output flip-flopxe2x80x9d and xe2x80x9cthe time from when data is outputted from the data output flip-flop by the internal clock that has reached there to when the data reaches the external memoryxe2x80x9d should be larger than the data hold time of the external memory; second condition: a value obtained by subtracting the first value from xe2x80x9cthe time corresponding to one cycle of the external clockxe2x80x9d should be larger than the data setup time of the external memory; third condition: a value obtained by subtracting xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the input flip-flopxe2x80x9d from the sum of xe2x80x9cthe time from when the external clock is outputted from the clock generator to when it reaches the external memoryxe2x80x9d and xe2x80x9cthe hold time of data to be outputted from the external memory on receipt of the external clockxe2x80x9d and xe2x80x9cthe time from when the data is outputted to when it reaches the input flip-flopxe2x80x9d should be larger than the data hold time of the input flip-flop; and fourth condition: a value obtained by subtracting the sum of xe2x80x9cthe time from when the external clock is outputted from the clock generator Lo when it reaches the external memoryxe2x80x9d and xe2x80x9cthe output delay time of data to be outputted from the external memory on receipt of the external clockxe2x80x9d and xe2x80x9cthe time from when the data is outputted to when it reaches the input flip-flopxe2x80x9d from the sum of xe2x80x9cthe time corresponding to one cycle of the internal clockxe2x80x9d and xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the input flip-flopxe2x80x9d should be larger than the data setup time of the input flip-flop.
Accordingly, the present invention can provide an integrated circuit that performs appropriate data transfer and clock supply, without having a complicated circuit like the conventional circuit in which plural delay elements are inserted in plural signal paths. Especially, the present invention facilitates design of an integrated circuit that requires high-speed access such as a SDRAM.
Furthermore, another integrated circuit according to the present invention, which makes data access to an external memory in synchronization with a clock, comprises: a clock generator for generating the clock from data; at least one first clock buffer for driving the clock as an external clock; at least one second clock buffer for driving the clock as an internal clock; a clock output buffer for outputting the external clock to the external memory; a data output flip-flop for outputting data to be outputted to the external memory, in synchronization with the internal clock; a first input flip-flop for latching the data outputted from the external memory, by a feedback clock of the external clock inputted to the external memory; and a second input flip-flop for latching the data latched by the first input flip-flop, by the internal clock; wherein a value of a phase difference D obtained by subtracting xe2x80x9cthe time from when the external clock is outputted from the clock generator to when it reaches the clock output bufferxe2x80x9d from xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the data output flip-flopxe2x80x9d is set so as to satisfy conditions as follows: a first value obtained by subtracting xe2x80x9cthe time from when the external clock is outputted from the clock generator to when it reaches the external memoryxe2x80x9d from the sum of xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the data output flip-flopxe2x80x9d and xe2x80x9cthe time from when data is outputted from the data output flip-flop by the internal clock that has arrived, to when the data reaches the external memoryxe2x80x9d should be larger than the data hold time of the external memory; a value obtained by subtracting the first value from xe2x80x9cthe time corresponding to one cycle of the external clockxe2x80x9d should be larger than the data setup time of the external memory; a value obtained by subtracting xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the second input flip-flopxe2x80x9d from a value V obtained by summing xe2x80x9cthe time during which the external clock is outputted from the clock generator to reach the external memory, and turns back from the external memory as a feedback clock to reach the first input flip-flopxe2x80x9d and xe2x80x9cthe cell delay of the first input flip-flopxe2x80x9d and xe2x80x9cthe wiring delay from the first input flip-flop to the second input flip-flopxe2x80x9d should be larger than the hold time of the second input flip-flop; a value obtained by subtracting the value V from the sum of xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the second input flip-flopxe2x80x9d and xe2x80x9cthe time corresponding to one cycle of the external clockxe2x80x9d should be larger than the setup time of the second input flip-flop; the value V should be larger than xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the second input flip-flop; and a value obtained by subtracting xe2x80x9cthe time from when the external clock is fed back from the external memory to when it reaches the first input flip-flopxe2x80x9d from xe2x80x9cthe time from when data is outputted from the external memory to when it reaches the first input flip-flopxe2x80x9d should be larger than the hold time of the first input flip-flop.
Accordingly, the present invention can provide an integrated circuit that makes access to the external memory using the feedback clock of the external clock.
The integrated circuit further comprises a phase difference detection circuit wherein plural sets of first phase differences and second phase differences are set in advance, the second phase difference being a phase difference between the point of time when the external clock is outputted from the integrated circuit and the point of time when the external clock reaches the integrated circuit by feedback from the external memory, and the first phase difference satisfying the above-mentioned conditions with respect to the second phase difference, and the phase difference detection circuit detecting an actual second phase difference after the integrated circuit is mounted on an arbitrary system, and then selecting a first phase difference corresponding to the detected result; and the first and/or second clock buffer is provided with delay elements corresponding to the respective first phase differences which have previously been set, and the delay elements are selected on the basis of the first phase difference selected by the phase difference detection circuit.
Since the integrated circuit is provided with the detector for detecting a phase difference between the external clock to be outputted to the external memory and the feedback clock from the external memory, the interface circuit can detect an actual delay and adjust the phase difference between the internal clock and the external clock. Further, even when there are various external factors, such as the wiring delay of a system on which the integrated circuit is mounted, the external load capacity, and the like, the optimum clock phase is adjusted.
The integrated circuit further comprises: as the input flip-flop, a first input flip-flop for latching the data outputted from the external memory, and a second input flip-flop for latching the data latched by the first input flip-flop; and as the second clock buffer, a clock buffer for supplying a first internal clock to the data output flip-flop and to the second input flip-flop, and a clock buffer for supplying a second internal clock to the first input flip-flop; wherein a value of a phase difference D0 obtained by subtracting xe2x80x9cthe time from when the external clock is outputted from the clock generator to when it reaches the external clock output bufferxe2x80x9d from xe2x80x9cthe time from when the first internal clock is outputted from the clock generator to when it reaches the data output flip-flopxe2x80x9d is set so as to satisfy the first and second conditions; and a phase difference D1 obtained by subtracting xe2x80x9cthe time from when the external clock is outputted from the clock generator to when it reaches the external clock output bufferxe2x80x9d from xe2x80x9cthe time from when the second internal clock is outputted from the clock generator to when it reaches the first input flip-flopxe2x80x9d, which phase difference D1 satisfies the third and fourth conditions, is set so that a value obtained by subtracting xe2x80x9cthe delay of the data inputted to the first input flip-flop until it reaches the second input flip-flopxe2x80x9d from a phase difference between the phase difference D0 and the phase difference D1 should be larger than the setup time of the second input flip-flop.
Accordingly, the present invention can provide an integrated circuit that constitutes a system for exchanging data at a higher speed clock, without having a complicated circuit in which plural delay buffers are inserted in plural positions like the conventional one. Especially, an integrated circuit having an interface circuit that requires high-speed access such as a SDRAM can easily be designed.
A clock phase adjustment method according to the present invention is used when an arbitrary device makes data access to an external memory in synchronization with a clock, and this method comprises: a step of extracting time parameters relating to transmission of signals in the device and transmission of signals between the device and the external memory, from the layout of the device when designing the device; a step of calculating, on the basis of the parameters, a first phase difference between the point of time when an external clock to be supplied to the external memory is outputted and the point of time when an internal clock for operating the device reaches a reference point of data input/output; a step of calculating, on the basis of the parameters, the range of the first phase difference which satisfies the condition that the external memory can capture data outputted from the device and the device can capture data outputted from the external memory; a step of judging whether the calculated first phase difference satisfies the calculated range of the first phase difference; a step of selecting an arbitrary first phase difference from the calculated range when it is judged in the judgement step that the calculated first phase difference does not satisfy the calculated range of the first phase difference: and a step of changing the value of delay of the external clock signal or the internal clock signal in the device, when designing the device, on the basis of the selected first phase difference.
Accordingly, when performing layout design of a device that makes access to an external memory using a clock, for example, when performing clock skew adjustment, the clock phase can be adjusted by changing the delay of the clock signal. Therefore, a circuit that can make reliable data access with an external memory is created without adjusting the clock phase by trial and error like the conventional one, and without performing a test for clock phase adjustment. Especially, even when high-speed access is required like a SDRAM, the present invention realizes easy and accurate phase adjustment between an external clock and an internal clock of a device capable of high-speed access. Further, since the circuit scale and the number of steps in circuit fabrication are reduced, the power consumption is reduced. Furthermore, since the design is easy, the time period for development is reduced, and automation is realized, whereby simple mistake in design is avoided.
Further, the first phase difference is a value obtained by subtracting xe2x80x9cthe time from when the external clock is outputted from a clock generator in the device to when it reaches an external clock output buffer in the devicexe2x80x9d from xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches a data output flip-flop in the device; and in the step of calculating the range of the first phase difference, the range of the first phase difference that satisfies the following first to fourth conditions is calculated: first condition: a first value obtained by subtracting xe2x80x9cthe time from when the external clock is outputted from the clock generator to when it reached the external memoryxe2x80x9d from the sum of xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the data output flip-flopxe2x80x9d and xe2x80x9cthe time from when data is outputted from the data output flip-flop by the internal clock to when the data reaches the external memoryxe2x80x9d should be larger than the data hold time that is required for the external memory to capture the data; second condition: a value obtained by subtracting the first value from xe2x80x9cthe time corresponding to one cycle of the external clockxe2x80x9d should be larger than the data setup time that is required for the external memory Lo capture the data; third condition: a value obtained by subtracting xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the input flip-flopxe2x80x9d from the sum of xe2x80x9cthe time from when the external clock is outputted from the clock generator to when it reaches the external memoryxe2x80x9d and xe2x80x9cthe hold time of data to he outputted from the external memory on receipt of the external clockxe2x80x9d and xe2x80x9cthe time from when the data is outputted to when it reaches the input flip-flop in the devicexe2x80x9d should be larger than the data hold time of the input flip-flop; and fourth condition: a value obtained by subtracting the sum of xe2x80x9cthe time from when the external clock is outputted from the clock generator to when it reaches the external memoryxe2x80x9d and xe2x80x9cthe output delay time of data to be outputted from the external memory on receipt of the external clockxe2x80x9d and xe2x80x9cthe time from when the data is outputted to when it reaches the input flip-flopxe2x80x9d from the sum of xe2x80x9cthe time corresponding to one cycle of the internal clockxe2x80x9d and xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the input flip-flopxe2x80x9d should be larger than the data setup time of the input flip-flop.
Furthermore, the first phase difference is a value obtained by subtracting xe2x80x9cthe time from when the external clock is outputted from a clock generator in the device to when it reaches an external clock output buffer in the devicexe2x80x9d from xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches a data output flip-flop in the device; data outputted from the external memory is latched into a first input flip-flop in the device by a clock that is the external clock inputted to the external memory and fed back to the device, and the latched data is latched into a second input flip-flip in the device by the internal clock; and in the process of calculating the range of the first phase difference, the range of the first phase difference that satisfies the following conditions is calculated: a first value obtained by subtracting xe2x80x9cthe time from when the external clock is outputted from the clock generator to when it reaches the external memoryxe2x80x9d from the sum of xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the data output flip-flopxe2x80x9d and xe2x80x9cthe time from when data is outputted from the data output flip-flop by the internal clock to when the data reaches the external memoryxe2x80x9d should be larger than the data hold time that is required for the external memory to capture the data; a value obtained by subtracting the first value from xe2x80x9cthe time corresponding to one cycle of the external clockxe2x80x9d should be larger than the data setup time that is required for the external memory to capture the data; a value obtained by subtracting xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the second input flip-flopxe2x80x9d from a value V obtained by summing xe2x80x9cthe time during which the external clock is outputted from the clock generator to reach the external memory, and turns back from the external memory as a feedback clock to reach the first input flip-flopxe2x80x9d and xe2x80x9cthe cell delay of the first input flip-flopxe2x80x9d and xe2x80x9cthe wiring delay from the first input flip-flop to the second input flip-flopxe2x80x9d should be larger than the hold time of the second input flip-flop; a value obtained by subtracting the value V from the sum of xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the second input flip-flopxe2x80x9d and xe2x80x9cthe time corresponding to one cycle of the external clockxe2x80x9d should be larger than the setup time of the second input flip-flop; the value V should be larger than xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the second input flip-flop; and a value obtained by subtracting xe2x80x9cthe time from when the external clock is fed back from the external memory to when it reaches the first input flip-flopxe2x80x9d from xe2x80x9cthe time from when data is outputted from the external memory to when it reaches the first input flip-flopxe2x80x9d should be larger than the hold time of the first input flip-flop.
Thereby, phase adjustment of a device that makes access to an external memory using a feedback clock can be performed when the device is designed.
Furthermore, another clock phase adjustment method according to the present invention is used when an arbitrary device makes data access to an external memory in synchronization with a clock, and this method comprises: a step of extracting time parameters relating to transmission of signals in the device and transmission of signals between the device and the external memory, from the layout of the device when designing the device; a step of calculating, on the basis of the parameters, the range of a first phase difference that is obtained by subtracting xe2x80x9cthe time from when the external clock is outputted from a clock generator in the device to when it reaches an external clock output buffer in the devicexe2x80x9d from xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches a data output flip-flop in the devicexe2x80x9d; a step of arbitrarily setting a plurality of second phase differences between the point of time when the external clock is outputted from the device and the point of time when the external clock, which is fed back from the external memory, reaches the device; a step of setting a first phase difference from the calculated range, corresponding to each of the plural second phase differences; a step of detecting an actual second phase difference after the device is mounted on an arbitrary system; a step of comparing the detected result with the set second phase differences, and selecting the corresponding first phase difference; and a step of changing the value of delay of the external clock signal or the internal clock signal in a clock buffer in the device, on the basis of the selected first phase difference; wherein data outputted from the external memory is latched into a first input flip-flop in the device by a clock that is the external clock inputted to the external memory and fed back to the device, and the latched data is latched into a second input flip-flop by the internal clock; in the step of calculating the range of the first phase difference, the range of the first phase difference that satisfies the following conditions is calculated: a first value obtained by subtracting xe2x80x9cthe time from when the external clock is outputted from the clock generator to when it reaches the external memoryxe2x80x9d from the sum of xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the data output flip-flopxe2x80x9d and xe2x80x9cthe time from when data is outputted from the data output flip-flop by the internal clock to when the data reaches the external memoryxe2x80x9d should he larger than the data hold time that is required for the external memory to capture the data; a value obtained by subtracting the first value from xe2x80x9cthe time corresponding to one cycle of the external clockxe2x80x9d should be larger than the data setup time that is required for the external memory to capture the data; a value obtained by subtracting xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the second input flip-flopxe2x80x9d from a value V obtained by summing xe2x80x9cthe time during which the external clock is outputted from the clock generator to reach the external memory, and turns back from the external memory as a feedback clock to reach the first input flip-flopxe2x80x9d and xe2x80x9cthe cell delay of the first input flip-flopxe2x80x9d and xe2x80x9cthe wiring delay from the first input flip-flop to the second input flip-flopxe2x80x9d should be larger than the hold time of the second input flip-flop; a value obtained by subtracting the value V from the sum of xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the second input flip-flopxe2x80x9d and xe2x80x9cthe time corresponding to one cycle of the external clockxe2x80x9d should be larger than the setup time of the second input flip-flop; the value V should be larger than xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the second input flip-flop; and a value obtained by subtracting xe2x80x9cthe time from when the external clock is fed back from the external memory to when it reaches the first input flip-flopxe2x80x9d from xe2x80x9cthe time from when data is outputted from the external memory to when it reaches the first input flip-flopxe2x80x9d should be larger than the hold time of the first input flip-flop.
That is, it is possible to design a device that detects the phase difference between an external clock to be outputted to an external memory and a feedback clock from the external memory, and adaptively adjusts the phase difference between the internal clock and the external clock. Accordingly, even when there are various external factors such as the wiring delay of a system on which the device is mounted, the external load capacity, and the like, an optimum clock phase can be set.
Furthermore, the above-described device is provided with, as the input flip-flop, a first input flip-flop that latches the data outputted from the external memory, and a second input flip-flop that latches the data latched by the first input flip-flop; the clock generator generates a first internal clock to be supplied to the date output flip-flop and the second input flip-flop, and a second internal clock to be supplied to the first input flip-flop; the first phase difference includes a phase difference D0 obtained by subtracting xe2x80x9cthe time from when the external clock is outputted from the clock generator to when it reaches the external clock output bufferxe2x80x9d from xe2x80x9cthe time from when the first internal clock is outputted from the clock generator to when it reaches the data output flip-flopxe2x80x9d, and a phase difference D1 obtained by subtracting xe2x80x9cthe time from when the external clock is outputted from the clock generator to when it reaches the external clock output butterxe2x80x9d from xe2x80x9cthe time from when the second internal clock is outputted from the clock generator to when it reaches the first input flip-flopxe2x80x9d; the step of calculating the range of the first phase difference calculates the range of the phase difference D0 that satisfies the first and second conditions, and the range of the first phase difference D1 that satisfies the third and fourth conditions, and calculates the ranges of the phase differences D0 and D1 which satisfy the condition that a value obtained by subtracting xe2x80x9cthe delay of the data inputted to the first input flip-flop until it reaches the second input flip-flopxe2x80x9d from the phase difference between the phase differences D0 and D1 should be larger than the setup time of the second input flip-flop; and the step of changing the value of delay of the clock signal changes the value of delay of the external clock or the internal clock in the device, on the basis of the phase difference between the selected phase differences D0 and D1.
Accordingly, the phase of a device that makes access to an external memory using a higher speed click can be adjusted. Especially, this method is effective when high-speed access like a SDRAM is required.
Furthermore, an integrated circuit design method according to the present invention is a method for designing an integrated circuit that makes data access to an external memory in synchronization with a clock, and the integrated circuit comprises: a clock generator for generating an internal clock and an external clock; a data output flip-flop for latching the data to be outputted to the external memory; a first input flip-flop for latching the data outputted from the external memory, by a feedback clock of the external clock inputted to the external memory; a second input flip-flop for latching the data latched by the first input flip-flop, by the internal clock; a phase difference detection circuit wherein plural sets of first phase differences and second phase differences are set in advance, the first phase difference being a phase difference obtained by subtracting xe2x80x9cthe time from when the external clock is outputted from the clock generator in the integrated circuit to when it reaches an external clock output buffer in the integrated circuitxe2x80x9d from xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches a data output flip-flop in the integrated circuitxe2x80x9d, and the second phase difference being a phase difference between the point of time when the external clock is outputted from the integrated circuit and the point of time when the external clock reaches the integrated circuit by feedback from the external memory, and the phase difference detection circuit detecting an actual second phase difference after the integrated circuit is mounted on an arbitrary system, and then selecting a first phase difference corresponding to the detected result; and a clock buffer including delay elements corresponding to the respective first phase differences that have previously been set, and selecting the delay elements on the basis of the first phase difference selected by the phase error detection circuit; and the design method comprises: a step of extracting time parameters relating to transmission of signals in the device and transmission of signals between the device and the external memory, from the layout of the device when designing the device; a step of calculating, on the basis of the parameters, the range of the first phase difference that satisfy the following conditions: a first value obtained by subtracting xe2x80x9cthe time from when the external clock is outputted from the clock generator to when it reaches the external memoryxe2x80x9d from the sum of xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the data output flip-flopxe2x80x9d and xe2x80x9cthe time from when data is outputted from the data output flip-flop by the internal clock to when the data reaches the external memoryxe2x80x9d should be larger than the data hold time that is required for the external memory to capture the data; a value obtained by subtracting the first value from xe2x80x9cthe time corresponding to one cycle of the external clockxe2x80x9d should be larger than the data setup time that is required for the external memory to capture the data; a value obtained by subtracting xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the second input flip-flopxe2x80x9d from a value V obtained by summing xe2x80x9cthe time during which the external clock is outputted from the clock generator to reach the external memory, and turns back from the external memory as a feedback clock to reach the first input flip-flopxe2x80x9d and xe2x80x9cthe cell delay of the first input flip-flopxe2x80x9d and xe2x80x9cthe wiring delay from the first input flip-flop to the second input flip-flopxe2x80x9d should be larger than the hold time of the second input flip-flop; a value obtained by subtracting the value V from the sum of xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the second input flip-flopxe2x80x9d and xe2x80x9cthe time corresponding to one cycle of the external clockxe2x80x9d should be larger than the setup time of the second input flip-flop; the value V should be larger than xe2x80x9cthe time from when the internal clock is outputted from the clock generator to when it reaches the second input flip-flop; and a value obtained by subtracting xe2x80x9cthe time from when the external clock is fed back from the external memory to when it reaches the first input flip-flopxe2x80x9d from xe2x80x9cthe time from when data is outputted from the external memory to when it reaches the first input flip-flopxe2x80x9d should be larger than the hold time of the first input flip-flop; and a step of arbitrarily setting a plurality of second phase differences; a step of setting a first phase difference that satisfies the above conditions, corresponding to each of the plural second phase differences; and a step of setting the value of delay of the external clock or the internal clock in the integrated circuit, corresponding to each of the calculated first phase differences.
That is, it is possible to design an integrated circuit that detects the phase difference between an external clock to be outputted to an external memory and a feedback clock from the external memory, and automatically adjusts the phase difference between the internal clock and the external clock, after the integrated circuit is mounted. Accordingly, even when there are various external factors such as the wiring delay of a system on which the device is mounted, the external load capacity, and the like, an optimum clock phase can be adjusted.